The present invention relates to a memory shared notably by several processors integrated into one and the same circuit based on semiconductors. The shared memory finds its application notably in the field of microelectronics.
In a multiprocessor system, the processors can work in parallel on one and the same application. It is therefore necessary for the processors to be able to exchange a considerable amount of data between themselves. In order to reduce the data transfer time between the processors, it is advantageous for all the processors to have access to one and the same memory. A first processor can thus work on a first task and then update first data in the memory as a function of the results that it has obtained. Thereafter it can signal to a second processor that the first data of the memory are ready to undergo another processing. The second processor can then use the first data of the memory in a second task. During this time, the first processor can process other data.
So that the sharing of the memory by several processors does not slow down the processing of the processors, a known scheme is to divide the memory into several independent memory banks. In this way, as long as the processors each work with a different memory bank, the sharing of the memory does not slow down their processing.
It is advisable for a shared memory such as this to use a design which allows both a reduction in production costs and optimization of the data transfer rates.
An existing solution uses multiplexers connected at their output to an input of the memory banks. The inputs of the multiplexers are connected to the outputs of the various processors requiring access to the memory. An input data bus of each processor is connected to an output of a multiplexer receiving as input the output data buses of all the memory banks.
A problem encountered with this implementation is the considerable number of connections required. In particular, there are a considerable number of connections linking the output data buses of the memory banks with the multiplexers situated on the input data buses of the processors. The surface area of these connections may be greater than the surface area of the memories and the total surface area of the shared memory may thus be doubled. Such an increase in the surface area of a shared memory gives rise to considerable production costs. Moreover the considerable length of these connections induces notably a considerable stray capacitance. This stray capacitance can slow the transfer of data and cause considerable energy consumption.
Another existing solution is to connect several processors to one and the same multi-port memory. A multi-port memory is a memory comprising a number k of inputs/outputs. The multi-port memory comprises for example several memory cells, each memory cell comprising a number k of switches. The k switches of each memory cell make it possible to connect each memory cell to a memory output data bus, from among k memory output data buses. Such a memory allows k processors to have access to said memory. However this other solution also requires a considerable number of connections. This implies that a component integrating such a memory is of relatively considerable size.